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Three-dimensional (3D) integration is pointed out as a potential street for non-stop functionality development in built-in circuits (IC) because the traditional scaling method is confronted with extraordinary demanding situations in primary and fiscal limits. Wafer point 3D IC can take numerous types, and so they often comprise a stack of numerous thinned IC layers which are vertically bonded and interconnected by way of via silicon through TSV.

There is an extended string of advantages that it is easy to derive from 3D IC implementation reminiscent of shape issue, density multiplication, more advantageous hold up and tool, more suitable bandwidth, and heterogeneous integration. This e-book offers contributions by means of key researchers during this box, overlaying motivations, know-how structures, purposes, and different layout concerns.

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3D-IC with through-silicon via (TSV) interconnects provides another path towards “More Moore” and “More than Moore” with relatively smaller capital investments. The 3D-IC approach using TSV interconnects, which provides electrical pathways through the thickness of a Si die, calls for a combination of via processes, extreme wafer thinning, and various wafer-to-wafer and chipto-wafer bonding techniques with thin wafer handling mechanisms. There are various factors related to device integration, which should be considered before adopting TSV technology design.

It is shown that advanced direct bond technology is an ideal solution for the requirements of a bond technology platform for 3D integration. Enquist et al. from Ziptronix will discuss advanced direct bond technology in this chapter. It is important to decrease the process temperature to around room temperature for application-oriented discrete system packaging, which requires three-dimensional interconnections between diverse substrates. In Chapter 10, Shigetou et al. 75in 280711-ch01 22 3D Integration Technology - Introduction and Overview beam irradiation process.

9 For existing microprocessor architectures, the off-chip bandwidth limitations have become quite prominent. , logic with DRAM). Heterogeneous integration of cache layers can enable denser, higher-performance, or more power-efficient levels in the memory hierarchy. Emerging nonvolatile memory stacking and DRAM and embedded DRAM stacks are under investigation. 5 Through-silicon vias or via-farm areas are likely to compromise the inherent density advantages of existing DRAM organizations. Furthermore, the TSV process limits the integration of vendor DRAM with microprocessor systems.

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